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Work experience: 
06/2001 to 07/2007
Design engineer
Location: 
Full time
Design of systems on silicon (DS2)

ASIC design for power-line communications modem
• Block description and verification with Verilog
• Functional validation of integrated circuit

09/2015 to 06/2016
System modelling consultant
Location: 
Full time
Intel
  • SystemC simulation specification and development with Intel CoFluent
  • Scoreboard responsible and develop C++ scoreboard classes
  • Responsible of test launching scripts and result analysis
07/2011 to 07/2015
FPGA engineer
Location: 
Full time
Marvell technology

• Automatize FPGA implementation flow and result analysis
• Used technology: Xilinx Virtex5 and Virtex6 on Synopsys HAPS and custom boards
• FPGA prototype synthesis and implementation to multi-FPGA platform
• Clock, reset and IO architecture design for FPGA with System Verilog
• Prototype start-up and low level debug support

06/2016
Design engineer
Location: 
Full time
ON-semiconductor
  • Design and verification System Verilog for DC-DC controller
  • Responsible of communication interfaces: SPI, I2C
  • Responsible of design checks: lint, CDC
08/2010 to 07/2011
Senior digital engineer
Location: 
Full time
Marvell technology

ASIC front-end tasks: JTAG, boundary-scan and memory BIST insertion

07/2007 to 08/2010
Senior design engineer
Location: 
Full time
Design of systems on silicon (DS2)

• Specification, development and verification of HW blocks with System Verilog
– Based in: generic TLM interfaces, use of types/structures/classes
– Divide in generic and reusable sub-blocks and communications
– Structured design and simulation
• Improvement of design flow with SystemC, for high level modeling:
– Specification, development and support of simulation environment
– Define TLM communication interfaces and develop the related generic classes
– Define and development of generic blocks
– Technical follow-up of share project with University of Cantabria

11/2000 to 06/2001
End of studies project
Location: 
Full time
Project work / diploma
Design of systems on silicon (DS2)

Interface for PCI connection developed with a commercial core (Verilog). It includes the verification with simulation and validation with FPGA prototypes.

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